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- ;*****************************************************************************
- ; Copyright Statement:
- ; --------------------
- ; This software is protected by Copyright and the information contained
- ; herein is confidential. The software may not be copied and the information
- ; contained herein may not be used or disclosed except with the written
- ; permission of MediaTek Inc. (C) 2011
- ;
- ;*****************************************************************************
- ;;================================================
- ;; PURPOSE: EVB Bring Up
- ;; CREATE_DATE: 2016/04/01
- ;; NOTE:
- ;;================================================
- ; Specify Core Number
- ;=================================================
- &NR_CPUS=1
- ; cluster 0 corebase: 0x8007000, 0x8007200, 0x8007400, 0x8007600
- ; cluster 1 corebase: 0x8009000, 0x8009200, 0x8009400, 0x8009600
- ;=================================================
- ; Initialize CPU
- ;=================================================
- &WDT_TEST=0
- if &WDT_TEST==0
- (
- RESET
- SYSTEM.OPTION ENRESET ON
- )
- SYSTEM.RESET
- SYSTEM.OPTION ENRESET ON
- SYSTEM.OPTION RESBREAK OFF
- SYSTEM.OPTION WAITRESET OFF
- SYSTEM.JTAGCLOCK 10.MHz;
- ;SYSTEM.CPU CortexA7MPCore
- SYStem.CPU CORTEXA53;
- ;R-T Memory Access
- SYSTEM.MULTICORE MEMORYACCESSPORT 0
- SYSTEM.MULTICORE DEBUGACCESSPORT 1
- ;SYSTEM.MULTICORE COREBASE APB:0x80070000
- ;Setting Core debug register access
- if &NR_CPUS==1
- (
- SYStem.CONFIG CORENUMBER 1;
- SYStem.CONFIG COREBASE 0x8D410000;
- SYStem.CONFIG CTIBASE 0x8D420000;
- )
- else
- (
- SYSTEM.CONFIG CORENUMBER 2;
- SYSTEM.CONFIG COREBASE 0x80810000 0x80910000;
- SYStem.CONFIG CTIBASE 0x80820000 0x80920000;
- )
- ;=================================================
- ; Attach and Stop CPU
- ;=================================================
- SYStem.Up
- wait 200.us
- SETUP.IMASKHLL ON
- SETUP.IMASKASM ON
- ;enable L2C 256KB
- D.S SD:0x102007F0 %LE %LONG 0x00010100 ;Enable L2C share SRAM (256K)
- D.S SD:0x102007F0 %LE %LONG 0x00010101 ;Enable L2C share SRAM (256K)
- ; set_hw_breakpoint_by_def
- ; setting attribute of breakpoints
- Break.Select Program OnChip
- Break.Select Hll OnChip
- Break.Select Spot OnChip
- Break.Select Read OnChip
- Break.Select Write OnChip
- PER.SET.FIELD SPR:0x30100 %LONG 0x1 0 ;Turn off MMU
- ; for pmic power latch (RGU + 0xA4)
- d.s c:0x100070a4 %le %long 0x66000001
- ; disable wdt (debug purpose)
- D.S SD:0x10007000 %LE %LONG 0x22000000
- ; Init DRAM
- ;do MT6765_FPGA_DDR
- print "loading pre-loader image"
- d.load.elf ../../../../../../../../out/target/product/evb6761_64_emmc/obj/PRELOADER_OBJ/bin/preloader_evb6761_64_emmc.elf
- Y.SPATH.RESET ; reset all source path
- Y.SPATH.SRD ../../platform/mt6761/src/init
- Y.SPATH.SRD ../../platform/mt6761/src/core
- Y.SPATH.SRD ../../platform/mt6761/src/drivers
- Y.SPATH.SRD ../../platform/mt6761/src/security
- Y.SPATH.SRD ../../platform/common
- Y.SPATH.SRD ../../custom/evb6761_64_emmc
- Break.Select Program OnChip
- Break.Select Hll OnChip
- Break.Select Spot OnChip
- Break.Select Read OnChip
- Break.Select Write OnChip
- R.S T 0
- ;winclear
- d.l
- enddo
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