mt_uart.h 8.6 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein is
  5. * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
  6. * the prior written permission of MediaTek inc. and/or its licensors, any
  7. * reproduction, modification, use or disclosure of MediaTek Software, and
  8. * information contained herein, in whole or in part, shall be strictly
  9. * prohibited.
  10. *
  11. * MediaTek Inc. (C) 2017. All rights reserved.
  12. *
  13. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  14. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  15. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
  16. * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
  17. * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
  18. * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
  19. * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
  20. * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
  21. * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
  22. * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
  23. * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
  24. * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
  25. * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
  26. * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  27. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
  28. * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
  29. * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
  30. * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
  31. * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  32. *
  33. * The following software/firmware and/or related documentation ("MediaTek
  34. * Software") have been modified by MediaTek Inc. All revisions are subject to
  35. * any receiver's applicable license agreements with MediaTek Inc.
  36. */
  37. /******************************************************************************
  38. *
  39. * Copyright Statement:
  40. * --------------------
  41. * This software is protected by Copyright and the information contained
  42. * herein is confidential. The software may not be copied and the information
  43. * contained herein may not be used or disclosed except with the written
  44. * permission of MediaTek Inc. (C) 2001
  45. *
  46. *******************************************************************************/
  47. #ifndef UART_HW_H
  48. #define UART_HW_H
  49. #include "platform.h"
  50. /* FCR */
  51. #define UART_FCR_FIFOE (1 << 0)
  52. #define UART_FCR_CLRR (1 << 1)
  53. #define UART_FCR_CLRT (1 << 2)
  54. #define UART_FCR_DMA1 (1 << 3)
  55. #define UART_FCR_RXFIFO_1B_TRI (0 << 6)
  56. #define UART_FCR_RXFIFO_6B_TRI (1 << 6)
  57. #define UART_FCR_RXFIFO_12B_TRI (2 << 6)
  58. #define UART_FCR_RXFIFO_RX_TRI (3 << 6)
  59. #define UART_FCR_TXFIFO_1B_TRI (0 << 4)
  60. #define UART_FCR_TXFIFO_4B_TRI (1 << 4)
  61. #define UART_FCR_TXFIFO_8B_TRI (2 << 4)
  62. #define UART_FCR_TXFIFO_14B_TRI (3 << 4)
  63. #define UART_FCR_FIFO_INIT (UART_FCR_FIFOE|UART_FCR_CLRR|UART_FCR_CLRT)
  64. #define UART_FCR_NORMAL (UART_FCR_FIFO_INIT | \
  65. UART_FCR_TXFIFO_4B_TRI| \
  66. UART_FCR_RXFIFO_12B_TRI)
  67. /* LCR */
  68. #define UART_LCR_BREAK (1 << 6)
  69. #define UART_LCR_DLAB (1 << 7)
  70. #define UART_WLS_5 (0 << 0)
  71. #define UART_WLS_6 (1 << 0)
  72. #define UART_WLS_7 (2 << 0)
  73. #define UART_WLS_8 (3 << 0)
  74. #define UART_WLS_MASK (3 << 0)
  75. #define UART_1_STOP (0 << 2)
  76. #define UART_2_STOP (1 << 2)
  77. #define UART_1_5_STOP (1 << 2) /* Only when WLS=5 */
  78. #define UART_STOP_MASK (1 << 2)
  79. #define UART_NONE_PARITY (0 << 3)
  80. #define UART_ODD_PARITY (0x1 << 3)
  81. #define UART_EVEN_PARITY (0x3 << 3)
  82. #define UART_MARK_PARITY (0x5 << 3)
  83. #define UART_SPACE_PARITY (0x7 << 3)
  84. #define UART_PARITY_MASK (0x7 << 3)
  85. /* MCR */
  86. #define UART_MCR_DTR (1 << 0)
  87. #define UART_MCR_RTS (1 << 1)
  88. #define UART_MCR_OUT1 (1 << 2)
  89. #define UART_MCR_OUT2 (1 << 3)
  90. #define UART_MCR_LOOP (1 << 4)
  91. #define UART_MCR_XOFF (1 << 7) /* read only */
  92. #define UART_MCR_NORMAL (UART_MCR_DTR|UART_MCR_RTS)
  93. /* LSR */
  94. #define UART_LSR_DR (1 << 0)
  95. #define UART_LSR_OE (1 << 1)
  96. #define UART_LSR_PE (1 << 2)
  97. #define UART_LSR_FE (1 << 3)
  98. #define UART_LSR_BI (1 << 4)
  99. #define UART_LSR_THRE (1 << 5)
  100. #define UART_LSR_TEMT (1 << 6)
  101. #define UART_LSR_FIFOERR (1 << 7)
  102. /* MSR */
  103. #define UART_MSR_DCTS (1 << 0)
  104. #define UART_MSR_DDSR (1 << 1)
  105. #define UART_MSR_TERI (1 << 2)
  106. #define UART_MSR_DDCD (1 << 3)
  107. #define UART_MSR_CTS (1 << 4)
  108. #define UART_MSR_DSR (1 << 5)
  109. #define UART_MSR_RI (1 << 6)
  110. #define UART_MSR_DCD (1 << 7)
  111. /* EFR */
  112. #define UART_EFR_EN (1 << 4)
  113. #define UART_EFR_AUTO_RTS (1 << 6)
  114. #define UART_EFR_AUTO_CTS (1 << 7)
  115. #define UART_EFR_SW_CTRL_MASK (0xf << 0)
  116. #define UART_EFR_NO_SW_CTRL (0)
  117. #define UART_EFR_NO_FLOW_CTRL (0)
  118. #define UART_EFR_AUTO_RTSCTS (UART_EFR_AUTO_RTS|UART_EFR_AUTO_CTS)
  119. #define UART_EFR_XON1_XOFF1 (0xa) /* TX/RX XON1/XOFF1 flow control */
  120. #define UART_EFR_XON2_XOFF2 (0x5) /* TX/RX XON2/XOFF2 flow control */
  121. #define UART_EFR_XON12_XOFF12 (0xf) /* TX/RX XON1,2/XOFF1,2 flow
  122. control */
  123. #define UART_EFR_XON1_XOFF1_MASK (0xa)
  124. #define UART_EFR_XON2_XOFF2_MASK (0x5)
  125. /* IIR (Read Only) */
  126. #define UART_IIR_NO_INT_PENDING (0x01)
  127. #define UART_IIR_RLS (0x06) /* Receiver Line Status */
  128. #define UART_IIR_RDA (0x04) /* Receive Data Available */
  129. #define UART_IIR_CTI (0x0C) /* Character Timeout Indicator */
  130. #define UART_IIR_THRE (0x02) /* Transmit Holding Register Empty
  131. */
  132. #define UART_IIR_MS (0x00) /* Check Modem Status Register */
  133. #define UART_IIR_SW_FLOW_CTRL (0x10) /* Receive XOFF characters */
  134. #define UART_IIR_HW_FLOW_CTRL (0x20) /* CTS or RTS Rising Edge */
  135. #define UART_IIR_FIFO_EN (0xc0)
  136. #define UART_IIR_INT_MASK (0x1f)
  137. /* RateFix */
  138. #define UART_RATE_FIX (1 << 0)
  139. //#define UART_AUTORATE_FIX (1 << 1)
  140. //#define UART_FREQ_SEL (1 << 2)
  141. #define UART_FREQ_SEL (1 << 1)
  142. #define UART_RATE_FIX_13M (1 << 0) /* means UARTclk = APBclk / 4 */
  143. #define UART_AUTORATE_FIX_13M (1 << 1)
  144. #define UART_FREQ_SEL_13M (1 << 2)
  145. #define UART_RATE_FIX_ALL_13M (UART_RATE_FIX_13M|UART_AUTORATE_FIX_13M| \
  146. UART_FREQ_SEL_13M)
  147. #define UART_RATE_FIX_26M (0 << 0) /* means UARTclk = APBclk / 2 */
  148. #define UART_AUTORATE_FIX_26M (0 << 1)
  149. #define UART_FREQ_SEL_26M (0 << 2)
  150. #define UART_RATE_FIX_ALL_26M (UART_RATE_FIX_26M|UART_AUTORATE_FIX_26M| \
  151. UART_FREQ_SEL_26M)
  152. #define UART_RATE_FIX_32M5 (0 << 0) /* means UARTclk = APBclk / 2 */
  153. #define UART_FREQ_SEL_32M5 (0 << 1)
  154. #define UART_RATE_FIX_ALL_32M5 (UART_RATE_FIX_32M5|UART_FREQ_SEL_32M5)
  155. #define UART_RATE_FIX_16M25 (0 << 0) /* means UARTclk = APBclk / 4 */
  156. #define UART_FREQ_SEL_16M25 (0 << 1)
  157. #define UART_RATE_FIX_ALL_16M25 (UART_RATE_FIX_16M25|UART_FREQ_SEL_16M25)
  158. /* Autobaud sample */
  159. #define UART_AUTOBADUSAM_13M 7
  160. #define UART_AUTOBADUSAM_26M 15
  161. #define UART_AUTOBADUSAM_52M 31
  162. //#define UART_AUTOBADUSAM_52M 29 /* 28 or 29 ? */
  163. #define UART_AUTOBAUDSAM_58_5M 31 /* 31 or 32 ? */
  164. /* VFIFO enable */
  165. #define UART_VFIFO_ON (1 << 0)
  166. #define UART_FCR_FIFOE (1 << 0)
  167. #define UART_FCR_FIFO_INIT (UART_FCR_FIFOE|UART_FCR_CLRR|UART_FCR_CLRT)
  168. typedef enum
  169. {
  170. UART1 = UART0_BASE,
  171. UART2 = UART1_BASE,
  172. UART3 = UART2_BASE,
  173. #ifdef UART3_BASE
  174. UART4 = UART3_BASE
  175. #endif
  176. } MT65XX_UART;
  177. #endif