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- /* Copyright Statement:
- *
- * This software/firmware and related documentation ("MediaTek Software") are
- * protected under relevant copyright laws. The information contained herein is
- * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
- * the prior written permission of MediaTek inc. and/or its licensors, any
- * reproduction, modification, use or disclosure of MediaTek Software, and
- * information contained herein, in whole or in part, shall be strictly
- * prohibited.
- *
- * MediaTek Inc. (C) 2017. All rights reserved.
- *
- * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
- * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
- * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
- * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
- * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
- * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
- * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
- * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
- * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
- * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
- * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
- * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
- * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
- * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
- * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
- * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
- * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
- * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
- *
- * The following software/firmware and/or related documentation ("MediaTek
- * Software") have been modified by MediaTek Inc. All revisions are subject to
- * any receiver's applicable license agreements with MediaTek Inc.
- */
- /******************************************************************************
- *
- * Copyright Statement:
- * --------------------
- * This software is protected by Copyright and the information contained
- * herein is confidential. The software may not be copied and the information
- * contained herein may not be used or disclosed except with the written
- * permission of MediaTek Inc. (C) 2001
- *
- *******************************************************************************/
- #ifndef UART_HW_H
- #define UART_HW_H
- #include "platform.h"
- /* FCR */
- #define UART_FCR_FIFOE (1 << 0)
- #define UART_FCR_CLRR (1 << 1)
- #define UART_FCR_CLRT (1 << 2)
- #define UART_FCR_DMA1 (1 << 3)
- #define UART_FCR_RXFIFO_1B_TRI (0 << 6)
- #define UART_FCR_RXFIFO_6B_TRI (1 << 6)
- #define UART_FCR_RXFIFO_12B_TRI (2 << 6)
- #define UART_FCR_RXFIFO_RX_TRI (3 << 6)
- #define UART_FCR_TXFIFO_1B_TRI (0 << 4)
- #define UART_FCR_TXFIFO_4B_TRI (1 << 4)
- #define UART_FCR_TXFIFO_8B_TRI (2 << 4)
- #define UART_FCR_TXFIFO_14B_TRI (3 << 4)
- #define UART_FCR_FIFO_INIT (UART_FCR_FIFOE|UART_FCR_CLRR|UART_FCR_CLRT)
- #define UART_FCR_NORMAL (UART_FCR_FIFO_INIT | \
- UART_FCR_TXFIFO_4B_TRI| \
- UART_FCR_RXFIFO_12B_TRI)
- /* LCR */
- #define UART_LCR_BREAK (1 << 6)
- #define UART_LCR_DLAB (1 << 7)
- #define UART_WLS_5 (0 << 0)
- #define UART_WLS_6 (1 << 0)
- #define UART_WLS_7 (2 << 0)
- #define UART_WLS_8 (3 << 0)
- #define UART_WLS_MASK (3 << 0)
- #define UART_1_STOP (0 << 2)
- #define UART_2_STOP (1 << 2)
- #define UART_1_5_STOP (1 << 2) /* Only when WLS=5 */
- #define UART_STOP_MASK (1 << 2)
- #define UART_NONE_PARITY (0 << 3)
- #define UART_ODD_PARITY (0x1 << 3)
- #define UART_EVEN_PARITY (0x3 << 3)
- #define UART_MARK_PARITY (0x5 << 3)
- #define UART_SPACE_PARITY (0x7 << 3)
- #define UART_PARITY_MASK (0x7 << 3)
- /* MCR */
- #define UART_MCR_DTR (1 << 0)
- #define UART_MCR_RTS (1 << 1)
- #define UART_MCR_OUT1 (1 << 2)
- #define UART_MCR_OUT2 (1 << 3)
- #define UART_MCR_LOOP (1 << 4)
- #define UART_MCR_XOFF (1 << 7) /* read only */
- #define UART_MCR_NORMAL (UART_MCR_DTR|UART_MCR_RTS)
- /* LSR */
- #define UART_LSR_DR (1 << 0)
- #define UART_LSR_OE (1 << 1)
- #define UART_LSR_PE (1 << 2)
- #define UART_LSR_FE (1 << 3)
- #define UART_LSR_BI (1 << 4)
- #define UART_LSR_THRE (1 << 5)
- #define UART_LSR_TEMT (1 << 6)
- #define UART_LSR_FIFOERR (1 << 7)
- /* MSR */
- #define UART_MSR_DCTS (1 << 0)
- #define UART_MSR_DDSR (1 << 1)
- #define UART_MSR_TERI (1 << 2)
- #define UART_MSR_DDCD (1 << 3)
- #define UART_MSR_CTS (1 << 4)
- #define UART_MSR_DSR (1 << 5)
- #define UART_MSR_RI (1 << 6)
- #define UART_MSR_DCD (1 << 7)
- /* EFR */
- #define UART_EFR_EN (1 << 4)
- #define UART_EFR_AUTO_RTS (1 << 6)
- #define UART_EFR_AUTO_CTS (1 << 7)
- #define UART_EFR_SW_CTRL_MASK (0xf << 0)
- #define UART_EFR_NO_SW_CTRL (0)
- #define UART_EFR_NO_FLOW_CTRL (0)
- #define UART_EFR_AUTO_RTSCTS (UART_EFR_AUTO_RTS|UART_EFR_AUTO_CTS)
- #define UART_EFR_XON1_XOFF1 (0xa) /* TX/RX XON1/XOFF1 flow control */
- #define UART_EFR_XON2_XOFF2 (0x5) /* TX/RX XON2/XOFF2 flow control */
- #define UART_EFR_XON12_XOFF12 (0xf) /* TX/RX XON1,2/XOFF1,2 flow
- control */
- #define UART_EFR_XON1_XOFF1_MASK (0xa)
- #define UART_EFR_XON2_XOFF2_MASK (0x5)
- /* IIR (Read Only) */
- #define UART_IIR_NO_INT_PENDING (0x01)
- #define UART_IIR_RLS (0x06) /* Receiver Line Status */
- #define UART_IIR_RDA (0x04) /* Receive Data Available */
- #define UART_IIR_CTI (0x0C) /* Character Timeout Indicator */
- #define UART_IIR_THRE (0x02) /* Transmit Holding Register Empty
- */
- #define UART_IIR_MS (0x00) /* Check Modem Status Register */
- #define UART_IIR_SW_FLOW_CTRL (0x10) /* Receive XOFF characters */
- #define UART_IIR_HW_FLOW_CTRL (0x20) /* CTS or RTS Rising Edge */
- #define UART_IIR_FIFO_EN (0xc0)
- #define UART_IIR_INT_MASK (0x1f)
- /* RateFix */
- #define UART_RATE_FIX (1 << 0)
- //#define UART_AUTORATE_FIX (1 << 1)
- //#define UART_FREQ_SEL (1 << 2)
- #define UART_FREQ_SEL (1 << 1)
- #define UART_RATE_FIX_13M (1 << 0) /* means UARTclk = APBclk / 4 */
- #define UART_AUTORATE_FIX_13M (1 << 1)
- #define UART_FREQ_SEL_13M (1 << 2)
- #define UART_RATE_FIX_ALL_13M (UART_RATE_FIX_13M|UART_AUTORATE_FIX_13M| \
- UART_FREQ_SEL_13M)
- #define UART_RATE_FIX_26M (0 << 0) /* means UARTclk = APBclk / 2 */
- #define UART_AUTORATE_FIX_26M (0 << 1)
- #define UART_FREQ_SEL_26M (0 << 2)
- #define UART_RATE_FIX_ALL_26M (UART_RATE_FIX_26M|UART_AUTORATE_FIX_26M| \
- UART_FREQ_SEL_26M)
- #define UART_RATE_FIX_32M5 (0 << 0) /* means UARTclk = APBclk / 2 */
- #define UART_FREQ_SEL_32M5 (0 << 1)
- #define UART_RATE_FIX_ALL_32M5 (UART_RATE_FIX_32M5|UART_FREQ_SEL_32M5)
- #define UART_RATE_FIX_16M25 (0 << 0) /* means UARTclk = APBclk / 4 */
- #define UART_FREQ_SEL_16M25 (0 << 1)
- #define UART_RATE_FIX_ALL_16M25 (UART_RATE_FIX_16M25|UART_FREQ_SEL_16M25)
- /* Autobaud sample */
- #define UART_AUTOBADUSAM_13M 7
- #define UART_AUTOBADUSAM_26M 15
- #define UART_AUTOBADUSAM_52M 31
- //#define UART_AUTOBADUSAM_52M 29 /* 28 or 29 ? */
- #define UART_AUTOBAUDSAM_58_5M 31 /* 31 or 32 ? */
- /* VFIFO enable */
- #define UART_VFIFO_ON (1 << 0)
- #define UART_FCR_FIFOE (1 << 0)
- #define UART_FCR_FIFO_INIT (UART_FCR_FIFOE|UART_FCR_CLRR|UART_FCR_CLRT)
- typedef enum
- {
- UART1 = UART0_BASE,
- UART2 = UART1_BASE,
- UART3 = UART2_BASE,
- #ifdef UART3_BASE
- UART4 = UART3_BASE
- #endif
- } MT65XX_UART;
- #endif
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